1. Field of the Invention
The present invention relates to a digital frequency divider with a phase control, and in particular to a frequency divider with a shift register.
2. Description of the Related Art
In digital systems, integrated circuits (ICs) or chips are operated by pulses from a clock. In systems such as television receivers or decrypters, there can be many different chips each operating at a different clock frequency. The different regions operating at different frequencies are referred to as xe2x80x9cclock domainsxe2x80x9d. For example, one chip may operate as a master chip in a 166 MHz domain, with another store chip in a 133 MHz domain. In this situation, there is a need for two clock frequencies.
One solution to the problem of providing different clock frequencies is to use a master frequency and produce the frequency for the store chip by dividing the master clock frequency.
We have appreciated that the frequency division should introduce a minimum noise into the clocking signal, and involve efficient use of circuitry. We have also appreciated that it would be useful to control the phase of a divided clock frequency. One known way of changing clock phase relative to one another is to use a delay line. However, we have appreciated that the maximum delays achievable with delay lines are small, and that they are prone to noise.
Accordingly, there is provided a digital frequency divider for dividing a clock frequency and having a variable phase output comprising:
a shift register for storing a bit sequence chosen according to a division factor and operating under control of a clock signal at a first frequency;
tap off circuitry arranged to tap the shift register at one or more variable points and arranged to produce two or more signals representative of the bit sequence;
control logic circuitry having at least two inputs arranged to receive the two or more signals representative of the bit sequence and arranged to provide at least two output signals; and
a multiplexer arranged to receive the two output signals and to select one of the output signals in turn under control of the clock signal at the first frequency to thereby produce a clock output signal at a second frequency being a division of the first frequency;
wherein the tap off circuitry and shift register are arranged such that the one or more tap off points of the shift register are variable in position along the bit sequence such that the clock output signal is variable in phase.
The combining of phase control with the circuitry of a frequency divider is an efficient use of circuitry. Moreover, the phase control is wholly digital and allows
infinite delay, both positive and negative, in either direction.